View ISL8216M_8907954.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 complete high voltage 80v, 4a dc/dc power module ISL8216M the ISL8216M is a simple and easy to use, high voltage dc/dc module and is ideal for a wide variety of applications. it eliminates design and manufacturing risks while dramatically improving time to market. the simplicity is in the "off-the-shelf" unassisted implementation. all you need is the ISL8216M, input and output capacitors, and one resistor to program the output voltage and you have a complete high voltage power design ready for the market. the ISL8216M is packaged in a thermally enhanced, compact (15mm15mm3.6mm) over-molded high-density array (hda) package, which permits full load operation without heat sink or fans. the package is suitable for automated assembly by standard surface mount equipment. the small amount of external components reduce the pcb to a component layer and a simple ground layer. related literature ? an190 7 ?ISL8216Meval1z evaluation board user?s guide? features ? complete switch mode power supply in one package ? wide input voltage range: 10v to 80v ? output current 4a ? programmable soft-start ? compliant with en 55022 class b (see an190 7 ) ? sync and adjustable frequency 200khz to 600khz ? single resistor sets v out +2.5v up to +30v ? setpoint accuracy 1.5% ? programmable overcurrent protection ? rohs compliant with exemption ? small footprint, low profile (15mm 15mm3.6mm) applications ? servers ? 48v telecom and datacom applications ? 12v and 42v automotive and industrial equipment ? distributed power converters and point-of-load (pol) regulation ? general purpose step-down dc/dc figure 1. typical application circuit figure 2. small footprint package with low profile (3.6mm) note: all pins not shown are floating 3.6mm 15mm 15mm may 9, 2014 fn8607.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2014. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL8216M 2 fn8607.2 may 9, 2014 submit document f eedbac k table of contents internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 recommended operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 efficiency performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 transient response performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 start-up performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 short circuit performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 programming the output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 enable/soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 oscillator and frequency synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 resistor between boot and v in for charging the bootstrap capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 power-good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 output capacitor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 thermal considerations and current derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 power loss curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 derating curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 layout guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 package description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 pcb layout pattern design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 thermal vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 stencil pattern design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 reflow parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
ISL8216M 3 fn8607.2 may 9, 2014 submit document f eedbac k internal block diagram ordering information part number ( no t es 1 , 2 , 3 ) part marking temp range (c) package (rohs compliant) pkg. dwg. # ISL8216Mirz ISL8216M -40 to +85 22 ld hda y22.15x15 ISL8216Meval1z evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb34 7 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets; molding compounds/die attach material s and nipdau plate - e4 termination finish, which is rohs compliant by eu exemption 7c-i and compatible with both snpb and pb-free soldering operati ons. intersil pb- free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020 3. for moisture sensitivity level (msl), please see product information page for isl82 1 6m . for more information on msl, please see tech brief tb363
ISL8216M 4 fn8607.2 may 9, 2014 submit document f eedbac k pin configuration ISL8216M (22 ld hda) top view
ISL8216M 5 fn8607.2 may 9, 2014 submit document f eedbac k pin descriptions pin number pin name type pin description a1 sgnd pwr control signal ground . all voltage levels are measured with respect to this pin. a3, b3 rtct i frequency setting pin . this pin sets the frequency of the sawtooth oscillator. the module has a resistor and a capacitor internally, which set the default frequency to 300khz. connect an external resistor to vin and an external capacitor to sgnd to change the frequency of the sawtooth oscillator. see ? oscillat or and f requency sync hr onization ? on page 1 2 . range: 0v to v in . a5 sync i signal synchronization . the switching frequency can be synchronized to an external clock through this pin. when the sync function is not used, this pin must be tied to ground. if the sync function is used, the rtct natural frequency must be set to a frequency lower than the sync input frequency. see ? oscillat or and f requency sync hr onization ? on page 1 2 . range: 0v to 5v. a7 vdd pwr power connection for the internal controller . tie to vin directly. a decoupling ceramic capacitor between this pin and signal ground (sgnd) is optional. a8 ocset i current limit sensing pin . the current limit can be reduced by placing a resistor, r ocset_ex , between this pin and vin. see ? ov er current pr o t ection ? on page 1 3 . range: 0v to v in . a11, f8 pgnd pwr power ground . these pins provides the power ground to the internal controller ic. tie these pins to the power ground plane through the lowest impedance connection. these pins are not internally connected to pad5. a12 pvcc pwr internal linear regulator output . typical: 11v. a14 ugate - test pin . this pin must be floating. avoid routing any trace close to this pin, as voltage on this pin can be as high as 100v. b1, c1 fb i feedback pin . output voltage is set by an external resistor between fb to sgnd. refer to equation 1 and t able 1 on page 10. typical: 1.2v c11 boot pwr floating bootstrap supply pin for the mosfet gate driver . the module has a bootstrap diode and a bootstrap capacitor internally. this pin can be used to provide an additional current path for charging the internal bootstrap capacitor; the charg ing current is derived from vin through a resistor. see figure 23, on page 1 4 . range: 0v to 92v. d1 comp i/o error amplifier output . this pin is connected to the output of the transconductance error amplifier and may be used to compensate the feedback loop. range: 0v to 12v. e1 pgood o power good . provides a power good status. an open drain output is asserted when the voltage at the fb pins is within 14% of the reference voltage. see ? p o w er-good ? on page 1 4 . range: 0v to 12v. e14 enss i/o enable and soft-start pin . this pin provides enable/disable functionality and soft-start timing functionality for the pwm output. connect a capacitor to sgnd to set the soft-start time. see ? enable/sof t-s tar t ? on page 11 . the module is disabled when this pin is held below 0.5v. to use this pin as an enable control pin, connect to a device with open drain output, or alternatively to an external enable control circuit, as shown in figure 1 8 . range: 0v to 5v. f1 pcompx i compensation adjustment pin . short this pin to vout if the output capacitors are all ceramic capacitors. connect a lower than 1k resistor to vout if the output capacitors are tantalum capacitors, polymer capacitors, or aluminum electrolytic capacitors. range: 1.2v to 30v. pad1 sgnd pwr signal ground of the internal controller . all voltage levels are measured with respect to this pad. this pad is electrically isolated. connect this pad to the signal ground plane using multiple vias for a robust thermal conduction path. pad2 vin pwr power input pin. apply input voltage between vin and p gnd (pad5). it is recommended to place an input decoupling capacitor directly between vin pin and pgnd. the input capacitor should be placed as closely as possible to the module. range: 10v to 80v. pad3 vout pwr power output pin . apply output load between vout and pgnd (pad5). place a high frequency output decoupling capacitor directly between vout and pgnd (pad5). the output capacitor should be placed as closely to the module as possible. range: 1.2v to 30v. pad4 phase pwr phase node . the phase pin should be floating. to achieve better thermal performance, the phase planes can also be used for heat removal with thermal vias connected to large inner layers. pad5 pgnd pwr power ground . power ground pins for both input and output returns. connect to power ground plane immediately below the module to maximize heat dissipation and to minimize the effect of switching noise and power loss due to the impedance of the copper traces.
ISL8216M 6 fn8607.2 may 9, 2014 submit document f eedbac k absolute maximum ratings thermal information input voltage (vin,vdd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100v boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105v enss pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6v fb, comp, sync pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8v phase ( no t e 4 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100v esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . 2kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 200v charge device model (tested per jesd22-c101c). . . . . . . . . . . . . . 750v latch up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) 22 ld hda ( no t es 5 , 6 ) . . . . . . . . . . . . . . . . 13 2.6 storage temperature range, (t stg ) . . . . . . . . . . . . . . . . -55c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating ratings input supply voltage (v in ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +10v to +80v vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +10v or +80v output voltage (v out ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.5v to +30v ambient temperature range (t a ) . . . . . . . . . . . . . . . . . . . -40c to +85c junction temperature range, (t j ) . . . . . . . . . . . . . . . . . . -40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. v ac (anode to cathode) specification for internal power diode. 5. ? ja is tested in free air with device mounted on a four-layer fr-4 test board (76.2x76.2x1.6mm) with 80% coverage, 2oz cu on top a nd bottom layers, plus two, buried, 1oz cu layers with coverage across the entire test board area. multiple vias were used, with via diameter = 0 .3mm on 1.2mm pitch. 6. for ? jc , the ?case? temperature is measured at the center of the package underside. electrical specifications t a = +25c. v in = 24v, v out = 12v, f sw = 300khz, c in = 1x100 f alum and 2x2.2 f ceramic, c out = 6x22 f ceremic, unless otherwise noted. parameter symbol conditions min ( no t e 7 )typ max ( no t e 7 ) units v dd supply bias voltage range 10 - 80 v bias supply current i vin v in = v dd = 24v, v out = 12v, i out = 0a - 14 - ma v dd shutdown current i vin_sd v in = v dd = 24v, enss = 0v - 20 - a internal linear regulator (pvcc) ( no t e 9 ) output voltage pvcc v dd = 15v to 80v, load = 3ma to 20ma - 10 - v maximum output current 20 - - ma short current protection -60-ma power-on reset ( no t e 9 ) rising v dd threshold 6.8 7.8 8.5 v falling v dd threshold - 220 - mv oscillator ( no t e 9 ) total variation on set frequency f sw = 300khz - +10 - % frequency range set by r t and c t . r t range = 20k to 100k, c t range = 470pf to 1200pf 200 - 600 khz sync frequency range above r t and c t natural frequency 200 - 600 khz ramp amplitude v osc v dd varied from 9.0v to 75v - 0.11*v in -v p-p min off time - 190 300 ns output characteristics output continuous current range iout (dc) 0-4a line regulation accuracy v out / v in v out = 12v, i out = 0a, v in = 15v - 75v - 0.005 - % v out = 12v, i out = 4a, v in = 15v - 75v - 0.005 - % load regulation accuracy v out / i out v in = 80v, c in = 2x100 f alum, 3x4.7 f ceramic capacitor, v out = 12v, c out = 2x100 f alum, 2x10 f ceramic capacitor, i out = 0a to 4a, f sw = 300khz". - - 0.15 %
ISL8216M 7 fn8607.2 may 9, 2014 submit document f eedbac k output ripple voltage v out i out = 4a, v out = 12v, v in = 24v, f sw = 400khz - 40 - mv p-p i out = 0a, v out = 12v, v in = 24v, f sw = 400khz - 10 - mv p-p i out = 4a, v out = 12v, v in = 80v, f sw = 400khz - 60 - mv p-p i out = 0a, v out = 12v, v in = 80v, f sw = 400khz - 20 - mv p-p dynamic characteristics voltage change for positive load step v out-dp i out = 1a to 4a. current slew rate = 2.5a/ s, v in = 24v, v out = 12v - 220 - mv p-p voltage change for negative load step v out-dn i out = 4a to 1a. current slew rate = 2.5a/ s, v in = 24v, v out = 12v - 180 - mv p-p reference voltage ( no t e 9 ) feedback voltage v fb - 1.192 - v accuracy -1.0 - +1.0 % enable/ss ( no t e 9 ) soft-start current i ss venss = 0v - 2 - a venss = 1.3v 22 33 43 a enable threshold v en voltage level where soft-start current changes from low-to-high 0.5 0.77 1.0 v maximum disable voltage v disen - - 0.5 v error amplifier ( no t e 9 ) transconductance 4.2 5.7 7.2 ms gain-bandwidth product ( no t e 1 0 ) gbw - 15 - mhz slew rate ( no t e 1 0 )sr -6-v/ s comp pin drive ( no t e 1 0 )i comp - 300 - a power good (open drain) ( no t e 9 ) power-good lower threshold v pg- percentage of nominal vfb; ~ 3 s noise filter 84 - 88 % power-good higher threshold v pg+ percentage of nominal vfb; ~ 3 s noise filter 112 - 116 % pgood leakage current i pglkg v pullup = 5.5v - - 1 a pgood voltage low i pgood = 4ma - - 0.5 v overcurrent protection ( no t e 9 ) dynamic current limit off-time t ocoff - 4 - ss cycle ocp (ocset) current source i ocset 89 104 119 a notes: 7. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 8. parameters with typ limits are not production tested unless otherwise specified. 9. parameters with min and/or max limits are 100% tested for internal ic prior to module assembly, unless otherwise specified. temperature limits established by characterization and are not production tested. 10. limits should be considered typical and are not production tested. electrical specifications t a = +25c. v in = 24v, v out = 12v, f sw = 300khz, c in = 1x100 f alum and 2x2.2 f ceramic, c out = 6x22 f ceremic, unless otherwise noted. (continued) parameter symbol conditions min ( no t e 7 )typ max ( no t e 7 ) units
ISL8216M 8 fn8607.2 may 9, 2014 submit document f eedbac k typical performance characteristics efficiency performance t a = +25c. the efficiency equation is as follows: figure 3. efficiency vs load current (5v out at 300khz) figure 4. efficiency vs load current (12v out ) figure 5. efficiency vs load current (24v out ) efficiency output power input power ----------------------------------------- p out p in --------------- - v out xi out ?? v in xi in ?? -------------------------------------- === 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 24v in to 5v out 300khz 36v in to 5v out 300khz 48v in to 5v out 300khz efficiency (%) load current (a) 60 65 70 75 80 85 90 95 100 0 1 2 3 4 80v in to 12v out 350khz 64v in to 12v out 350khz 36v in to 12v out 400khz 48v in to 12v out 400khz 24v in to 12v out 400khz efficiency (%) load current (a) 60 65 70 75 80 85 90 95 100 0 1 2 3 4 efficiency (%) load current (a) 80 vin to 24v out 350khz 48v in to 24v out 450khz 64v in to 24v out 400khz
ISL8216M 9 fn8607.2 may 9, 2014 submit document f eedbac k typical performance characteristics transient response performance c out = 6x22 f ceramic capacitors, i out = 1a to 4a, current slew rate = 2.5a/ s. t a = +25c. figure 6. 5v out transient response figure 7. 5v out transient response figure 8. 12v out transient response figure 9. 12v out transient response figure 10. 24v out transient response figure 11. 24v out transient response 50mv/div 1a/div 100 s/div v out i out v in = 24v v out = 5v f sw = 300khz 100 s/div 50mv/div 1a/div v out i out v out = 5v f sw = 300khz v in = 36v 50mv/div 1a/div 100 s/div i out v out v in = 24v v out = 12v f sw = 400khz 100mv/div 1a/div 100 s/div i out v out v in = 48v f sw = 350khz v out = 12v 200mv/div 1a/div i out v out 100 s/div v in = 64v v out = 24v f sw = 400khz 100 s/div 200mv/div 1a/div i out v out v in = 80v v out = 24v f sw = 400khz
ISL8216M 10 fn8607.2 may 9, 2014 submit document f eedbac k start-up performance t a = +25c, v in = 36v, v out = 12v, c in = 100 f alum, 4x2.2 f ceramic capacitors, c out = 6x22 f ceramic capacitors, css = 0.047 f, i out = 0a, 4a figure 12. start-up at 0a figure 13. start-up at 4a 2ms/div 5v/div 200ma/div v out i in v in = 36v v out = 12v i out = 0a 2ms/div 5v/div 500ma/div v out i in v in = 36v v out =12v i out = 4a short circuit performance t a = +25c, v in = 36v, v out = 12v, c in = 100 f alum, 4x2.2 f ceramic capacitors, c out = 6x22 f ceramic capacitors, i out = 0a, 4a figure 14. short circuit at 0a figure 15. short circuit at 4a 50 s/div 5v/div 1a/div v out i in v in = 36v v out = 12v i out = 0a 100 s/div 5v/div 1a/div v out i in v in = 36v v out = 12v i out = 4a
ISL8216M 11 fn8607.2 may 9, 2014 submit document f eedbac k application information programming the output voltage the ISL8216M has an internal 1.192v 1% reference voltage. programming the output voltage requires a resistor, r fb , between fb and sgnd. please note that the output voltage accuracy is also dependent on the resistance accuracy. the customer should select a high accuracy resistor (i.e. 0.5%) in order to achieve the overall output accuracy. the output voltage can be calculated as shown in equation 1 . the value of r fb for selecting different typical output voltages is shown in t able 1 . enable/soft-start figure 1 6 illustrates the start-up scheme of the ISL8216M. the power-on reset (por) function continually monitors the bias voltage at v dd and v in . when the voltage at v dd and v in exceed their rising por thresholds (t 0 ), the ISL8216M initially provides 2 a to charge the soft-start capacitor, c ss , connected to the enss pin. if the voltage at this pin is allowed to rise, it will ramp-up with at a slope determined by the 2 a current and the value of the soft-start capacitor. when the voltage at enss reaches 0.77v (typ) at t 1 , the oscillator circuit is active, causing the voltage at the rtct pin to drop from v in and generate a sawtooth waveform. at the same time, the soft-start current is increased to 33 a; as a result, the enss voltage then ramps up at a faster rate. the ugate starts switching when the enss voltage reaches 1.4v (typ). the delay from por (t 0 ) to the time the ic starts switching (t 2 ) can be approximated by using equation 2 : the output voltage soft-start time is determined by the rise time of enss voltage from 1.4v to 2.6v (t 3 - t 2 ). the output voltage ramp time can be calculated from: the soft-start capacitor c ss is continuously charged up linearly and clamped at 5v. note that any leakage current on the enss node will extend the start-up period. figure 1 7 shows the typical soft-start waveforms. the module can be enabled by an external signal by using an open-drain output device, or by adding an external circuit, as shown in figure 1 8 . for such circuit, a bias voltage of approximately 5.1v is recommended, which can be generated from v in simply through a resistor in series with a zener diode that has a nominal working voltage of 5.1v. when the external control signal is low, enss is pulled to ground. when the external control signal is high, enss is released to allow the soft-start function. table 1. value of rfb for different output voltages r fb ( ) typical v out (v) 3.48k 5 1.24k 12 715 20 590 24 464 30 v out 1 11.3k ? r fb ------------------- - + ?? ?? 1.192v ? = (eq. 1) 1v 2v 3v 4v 5v t 0 t 1 t 2 enss t 3 v out 2.6v 1.4v 0.7v por figure 16. typical soft-start diagram t delay switching ? 3.712 10 5 c ss ? ? = (eq. 2) t ss 1.2 33 6 ? ? 10 --------------------- - c ss ? = (eq. 3) rtct enss vout phase v out enss r t /c t phase figure 17. typical soft-start waveform figure 18. external enable circuit
ISL8216M 12 fn8607.2 may 9, 2014 submit document f eedbac k the selection of the resistor in series with the zener diode can be calculated as: where: ?v z is the zener diode?s working voltage, nominal 5.1v. ?i z is the zener diode?s working reverse current, typically about 5ma. power dissipation rating should be taken into consideration when selecting r z . oscillator and frequency synchronization the ISL8216M has an internally set fixed frequency of 300khz. by adding an external resistor (r t ) between v in and rtct pin and a capacitor (c t ) between rtct pin and sgnd, the ISL8216M can provide adjustable frequency from 200khz to 600khz. the time constant of r t /c t determines the oscillator frequency. the frequency setting curve is shown in figure 20 . note that any parasitic capacitance present on the rtct pin adds to the equivalent c t value and thus decreases the switching frequency. t able 2 provides frequency selection for optimum efficiency at typical v in and v out conditions and corresponding r t and c t values. note that when the controller is disabled, the voltage at rtct pin rises up to the input voltage. hence, the voltage rating of the c t capacitor must be sufficient to support the maximum input voltage. the sync pin provides the function to synchronize the ISL8216M?s switching frequency to an external source. when frequency synchronization is used, the time constant of r t /c t must be set longer than the period of the sync signal. when the external sync feature is not used, the customer should tie the sync pin to sgnd. table 2. switching frequency for optimum efficiency for different input and output voltages v in (v) v out (v) switching frequency (khz) r t c t 24 5 300 open open 36 5 300 open open 48 5 300 open open 24 12 400 143k open 54.9k 220pf 36 12 400 143k open 54.9k 220pf r z v in v z ? i z ---------------------- - = (eq. 4) 250 300 350 400 450 500 10 100 1k figure 19. r t and c t vs switching frequency switching frequency (khz) c t open c t = 220pf r 5 value (k ) 48 12 400 143k open 54.9k 220pf 64 12 400 143k open 54.9k 220pf 80 12 350 267k open 73.2k 220pf 48 24 450 95.3k open 43.2k 220pf 64 24 400 143k open 54.9k 220pf 80 24 350 267k open 73.2k 220pf table 2. switching frequency for optimum efficiency for different input and output voltages (continued) v in (v) v out (v) switching frequency (khz) r t c t phase r t /c t sync figure 20. synchronization operation
ISL8216M 13 fn8607.2 may 9, 2014 submit document f eedbac k minimum on-time the ISL8216M requires the internal mosfet to be turned on to a minimum of 200ns (typ). this minimum gate pulse width is required to ensure proper samplings of the overcurrent protection circuit. for low duty cycle applications, the switching frequency must be selected to satisfy the condition shown in equation 5 : where ? is converter efficiency. minimum off-time at the termination of the oscillator?s ramp, there is a 190ns time interval before the next ramp starts. this time interval creates the minimum-off time of the pwm. this period ensures that the boot capacitor charge is refreshed. equation 6 can be used to calculate the switching frequency to meet the condition: overcurrent protection the overcurrent protection function protects the module from overcurrent conditions by monitoring the current flowing through the mosfet. ocp (overcurrent protection) is implemented via a resistor (r ocset ) and a capacitor (c ocset ) connected between the ocset pin and the drain of the mosfet. an internal 104 a current source develops a voltage across r ocset , which is then compared with the drain-to-source voltage developed across the mosfet measured with regard to the phase node. when the drain-to-source voltage across the mosfet exceeds the voltage drop across the resistor r ocset , an ocp event occurs. c ocset is placed in parallel with r ocset to smooth the voltage across r ocset in the presence of switching noise on the input bus. the module has an internal resistor of 2k ; an external r ocset_ex can be added in between ocset and vin, and thus in parallel with the internal 2k , to further reduce the overcurrent limit. a 200ns blanking period is used to reduce the current sampling error due to leading-edge switching noise. the ocp trip point varies mainly due to mosfet r ds(on) variations and layout noise concerns. to avoid overcurrent tripping in the normal operating load range, find the r ocset_ex resistor from the equation 7 with: 1. the maximum r ds(on) at the highest junction temperature. 2. the minimum i ocset , 89 a. determine the overcurrent limit greater than the inductor peak current at the maximum output continuous current. if overcurrent is detected, the output immediately shuts off, it cycles the soft-start function in a hiccup mode (4 dummy soft-start time-outs, then up to one real one) to provide fault protection. if the shorted condition is not removed, this cycle will continue indefinitely. figures 2 1 and 22 illustrate typical waveforms during overcurrent protection. f osc v out ? v in ? ----------------- - 1 t on min ?? --------------------- - ? ? (eq. 5) f osc 1 v out ? v in ? ----------------- - ? ?? ?? ?? 1 t off min ?? ---------------------- ? ? (eq. 6) r ocset r ocset ex ? 2k ? ? r ocset ex ? 2k ? + ------------------------------------------------------ - i oc ? i l 2 -------- + ?? ?? r ds on ?? ? i ocset ---------------------------------------------------------- == (eq. 7) ? i l = v in - v out f sw l ? ------------------------------- - v out v in --------------- - ? ?? ?? ?? where: ?r ocset_ex is the external resistor between ocset and v in ?f sw is the switching frequency ? internal inductor l = 5.6 h nominal figure 21. typical overcurrent protection vout enss il v out enss l figure 22. typical hiccup recover vout enss il v out enss il
ISL8216M 14 fn8607.2 may 9, 2014 submit document f eedbac k resistor between boot and v in for charging the bootstrap capacitor the internal bootstrap diode connected to the pvcc pin provides charge for the internal bootstrap capacitor. for above 12v out applications, a resistor connecting between boot pin and vin pin is recommended for certain conditions. refer to t able 3 . this resistor provides additional bootstrap charge introduced from v in , which can ensure the gate drive circuit functions properly at very light load. see figure 23 for the recommended external resistor values at 20v out , 24v out , 27v out , and 30v out conditions. a minimum 0.25w power rating is recommended for this resistor. if such a resistor is used while an external control signal is used to enable the module, an external circuit is required to pull enss and v out to ground when the external control signal is low, as shown in figure 2 4 . the bias voltage in this circuit can be the same bias voltage as shown in figure 1 8 . without such a circuit, a residual voltage can be generated on v out through the path of v in , resistor, bootstrap diode, bootstrap capacitor, inductor and v out . power-good the pgood comparator monitors the voltage on the fb pin. pgood is asserted (open drain) when the fb pin voltage is within 14% of the reference voltage. the turn-on response of the pgood circuit has a typical 3 s delay. the pgood is de-asserted under disable, overcurrent event, or over-temperature event. for >12v out applications where v in power-up/down (module self enable/disable) is required and pgood signal is utilized, a pgood delay circuit and a 1k , 1w rating dummy load resistor are recommended. the pgood delay circuit is shown in figure 25 . note when the dummy load resistor is used, the resistor between v in and boot ( figure 23 ) is no longer required. during v in power-up (module self enable) for >12v out applications at very light load current, without such a delay circuit, v out may have a drop after initially reaching the target due to the lack of bootstrap charge. with such a delay circuit, the pgood signal can be delayed for 250ms. for applications of 12v out , the pgood delay circuit is not required. output capacitor selection an output capacitor is required to filter the output and supply the load transient current. the output capacitor can be a low esr tantalum capacitor, a low esr polymer capacitor, a low esr aluminum electrolytic capacitor, or all ceramic capacitors. internally optimized loop compensation provides sufficient stability margins for applications using different types of capacitors. a minimum total output capacitance of 120 f with low esr is recommended to meet the output voltage ripple and load transient requirements. use only specialized low-esr capacitors intended for switching regulator applications for the bulk capacitors. the bulk capacitor?s esr will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. an aluminum electrolytic capacitor's esr value is related to the case size with lower esr available in larger case sizes. however, the equivalent series inductance (esl) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. in most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. a high frequency ceramic decoupling capacitor can be placed between module?s v out and pgnd, as close to the module as possible, in order to decouple high frequency switching noise. high frequency ceramic decoupling capacitors should also be placed as close to the power pins of the load as possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load on specific decoupling requirements. 0 2 4 6 8 10 12 14 16 18 20 20 30 40 50 60 70 80 20v out v in (v) 24v out 27v out 30v out recommended resistor (k ) figure 23. recommended external resistor value from boot to pvin figure 24. external enable circuit while v in -boot resistor is used figure 25. pgood delay circuit
ISL8216M 15 fn8607.2 may 9, 2014 submit document f eedbac k input capacitor selection a combination of bulk capacitors and low equivalent series resistance (esr) ceramic capacitors are recommended as input capacitors. a bulk input capacitor(s) is needed to supply the current during output load transient conditions. the minimum required input bulk capacitance can be calculated as shown in equation 8 . where: ? v drop is the maximum allowable drop on the input voltage during output peak load transient. ?c min(bulk) is the minimum required bulk capacitance ( f). ? i in is the input transient current reflected from the output load transient current (a). ?l trace is the parasitic inductance of the trace connected to input supply due to pcb layout. typically 50nh. ? i o is the output load transient current (a). ? ?? is the efficiency of the converter (%). other important parameters for the bulk input capacitor are the voltage rating and the rms current rating. the capacitor voltage rating should be at least 1.25x greater than the maximum input voltage. a voltage rating of 1.5x greater is a conservative guideline. the rms current rating requirement for the total input capacitance is calculated approximately as shown in equation 9 . in addition to the bulk capacitance, low esr ceramic capacitance is recommended in order to reduce input voltage ripple and decouple between the vin and gnd of the module. this capacitance reduces voltage ringing created by the switching current across parasitic circuit elements. the ceramic capacitors should be placed as closely as possible to the module pins. the minimum required input ceramic capacitors can be calculated as shown in equation 1 0 . where: ?c min(cer) is the minimum required ceramic capacitance ( f) ?i o is the output current (a) ? d is the duty cycle, d = v out /v in ?f sw is the switching frequency (khz) ?v in(p-p) is the allowable peak-to-peak input voltage ripple (v) t he higher the ceramic capacitance, the less rms current the bulk capacitance is subject to, since the bulk capacitance typically has much higher esr than the ceramic capacitance. by increasing the ceramic capacitance, the rms current requirement for the bulk input capacitors can be reduced. a typical 4x2.2 f ceramic capacitance is recommended. for a through-hole design, several electrolytic capacitors in parallel may be needed. for surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. these capacitors must be capable of handling the surge-current at power-up. thermal protection if the ISL8216M?s junction temperature reaches a nominal temperature of +150c, the controller will be disabled. the ISL8216M will not be re-enabled until the junction temperature drops below +110c. thermal considerations and current derating experimental power loss curves ( figures 30 through 32 ), along with ? ja from thermal modeling analysis, can be used as a guide for thermal consideration for the module. the derating curves ( figures 33 through 42 ) are derived from the maximum power allowed while maintaining temperature below the maximum junction temperature of +115c. the maximum +115c junction temperature is considered for the module to load the current consistently and it provides 10c margin of safety from the rated junction temperature of +125c. if necessary, customers can adjust the margin of safety according to the real applications. in the actual application, other heat sources and design margins should be considered. c min bulk ?? 1.21 i in 2 ? ? l trace ? v drop ? -------------------------------------------------------- - = i in ? v out ? v in ? ------------------ - i o ? ? = (eq. 8) i cin rms ?? i o d1 d ? ?? = d v o v in --------- = (eq. 9) c min cer ?? i o d ? 1d ? ?? f sw v ? in p p ? ?? ------------------------------------------- = (eq. 10)
ISL8216M 16 fn8607.2 may 9, 2014 submit document f eedbac k typical application circuits table 3. external circuits requirement based on application conditions conditions external circuits requirements figures v out use pgood signal enable method pgood delay circuit 1k dummy load resistor v in -boot resistor - 12v no self or external enable control no no no figures 26 and 2 7 12v yes self or external enable control no no no figures 26 and 2 7 >12v no self or external enable control no no yes figure 28 >12v yes external enable control no no yes figure 28 >12v yes self enable yes yes no figure 29 figure 26. 24v in to 48 vin 5v out , 4a, 300khz note: ? if module is to be enabled by an external signal, an open drain device or an external enable circuit is required. refer to ? enable/sof t-s tar t ? on page 11 .
ISL8216M 17 fn8607.2 may 9, 2014 submit document f eedbac k figure 27. 24 vin to 80 vin , 12v out, 4a figure 28. 36 vin to 64 vin , 24v out , 4a, 400khz notes: ? if module is to be enabled by an external signal, an open drain device or an external enable circuit is required. refer to ? enable/sof t-s tar t ? on page 11 . ? refer to figure 19 and t able 2 for optimum switching frequency and r t and/or c t values. notes: ? if module is to be enabled by an external signal, an open drain device or an external enable circuit is required. refer to ? enable/sof t-s tar t ? on page 11 . ? refer to figure 19 and t able 2 for optimum switching frequency and r t and/or c t values. ? refer to figure 23 for vin-boot resistor (r boot ) value.
ISL8216M 18 fn8607.2 may 9, 2014 submit document f eedbac k figure 29. 80v in 24v out , 3a, 350khz, self enable, using pgood signal notes: ? for this condition (module self-enable, >12vout, using pgood), a pgood delay circuit, a 1k , 1w rating dummy load resistor, as well as a soft-start capacitor of at least 0.1 f are required. refer to ? p o w er-good ? on page 1 4 . the v in -boot resistor (r boot ) is not required when 1k dummy load resistor is present. ? refer to ? ov er current pr o t ection ? on page 1 3 for the external ocset resistor selection. ? refer to figure 19 and t able 2 for optimum switching frequency and r t and/or c t values.
ISL8216M 19 fn8607.2 may 9, 2014 submit document f eedbac k power loss curves figure 30. power loss vs load current (5v out ) for various input voltages figure 31. power loss vs load current (12v out ) for various input voltage figure 32. power loss vs load current (24v out ) for various input voltage 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 1 2 3 4 36v in 5v out 300khz 24v in 5v out 300khz load current (a) power loss (w) 0 1 2 3 4 5 6 7 8 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 36v in 12v out 400khz 24v in 12v out 400khz 80v in 12v out 350khz 64v in 12v out 350khz 48v in 12v out 400khz load current (a) power loss (w) 0 1 2 3 4 5 6 7 8 9 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 48v in 24v out 450khz 64v in 24v out 400khz 80v in 24v out 350khz load current (a) power loss (w)
ISL8216M 20 fn8607.2 may 9, 2014 submit document f eedbac k derating curves figure 33. derating curve 24v in to 5v out figure 34. derating curve 36v in to 5v out figure 35. derating curve 24v in to 12v out figure 36. derating curve 36v in to 12v out figure 37. derating curve 48v in to 12v out figure 38. derating curve 64v in to 12v out 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 65 75 85 95 105 115 ambient temperature(c) 0lfm 200lfm 400lfm load current (a) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 65 75 85 95 105 115 400lfm 200lfm 0lfm load current (a) ambient temperature(c) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 65 75 85 95 105 115 400lfm 200lfm 0lfm load current (a) ambient temperature(c) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 55 75 95 115 0lfm 200lfm 400lfm ambient temperature(c) load current (a) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 55 75 95 115 0lfm 200lfm 400lfm ambient temperature(c) load current (a) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 35 55 75 95 115 0lfm 200lfm 400lfm ambient temperature(c) load current (a)
ISL8216M 21 fn8607.2 may 9, 2014 submit document f eedbac k figure 39. derating curve 80v in to 12v out figure 40. derating curve 48v in to 24v out figure 41. derating curve 64v in to 24v out figure 42. derating curve 80v in to 24v out derating curves (continued) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 35 55 75 95 115 ambient temperature(c) load current (a) 0lfm 200lfm 400lfm 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 25 45 65 85 105 ambient temperature(c) load current (a) 0lfm 200lfm 400lfm 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 25 45 65 85 105 ambient temperature(c) load current (a) 0lfm 200lfm 400lfm 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 25 45 65 85 105 0lfm 200lfm 400lfm ambient temperature(c) load current (a)
ISL8216M 22 fn8607.2 may 9, 2014 submit document f eedbac k layout guide to achieve stable operation, low losses and good thermal performance, some layout considerations are necessary. ? vout, vin, phase, and gnd should have large copper areas for power path to minimize conduction loss and thermal stress. place enough thermal vias to connect the power planes in different layers under or around the module. ? establish a separate ground plane for sgnd (pin a1 and pad 1) and pgnd (pin f8, a11, and pad 5) and connect them at a single point as shown in figure 43 . this will help block the high frequency noise from entering the controller via sgnd. ? place at least one high frequency ceramic capacitor between (1) vin and pgnd, (2) vout and pgnd, and (3) pvcc and gnd, as closely to the module as possible in order to minimize high-frequency noise. ? avoid routing any sensitive signal traces, such as vout and fb near the phase pad. ? phase pad is a switching node that generates switching noise. keep the pad under the module. for noise-sensitive applications, it is recommended to keep phase pad only on the top and inner layers of the pcb. also, do not place phase pads exposed to the outside on the bottom layer of the pcb. package description the structure of ISL8216M belongs to the high density array (hda) package. this kind of package has advantages, such as good thermal and electrical conductivity, low weight and small size. the hda package is applicable for surface mounting technology. the ISL8216M contains several types of devices, including resistors, capacitors, inductors and control ics. the ISL8216M is a copper lead-frame based package with exposed copper thermal pads, which have good electrical and thermal conductivity. the copper lead frame and multi-component assembly is over-molded with polymer mold compound to protect these devices. the package outline, typical pcb layout pattern design, and typical stencil pattern design are shown in the ? p ac k age outline dra wing ? on page 25 . the module has a small size of 15mmx15mmx3.6mm. figure 44 shows typical reflow profile parameters. these guidelines are general design rules. users can modify parameters according to their application. pcb layout pattern design the bottom of the ISL8216M is a lead-frame footprint, which is attached to the pcb by surface mounting process. the pcb layout pattern is shown in the package outline drawing on page 29 . the pcb layout pattern is essentially 1:1 with the hda exposed pad and i/o termination dimensions. the thermal lands on the pcb layout should match 1:1 with the package exposed die pads. thermal vias a grid of 1.0mm to 1.2mm pitch thermal vias, which drops down and connects to buried copper plane(s), should be placed under the thermal land. the vias should be about 0.3mm to 0.33mm in diameter with the barrel plated to about 1.0 ounce copper. although adding more vias (by decreasing via pitch) will improve the thermal performance, diminishing returns will be seen as more and more vias are added. simply use as many vias as practical for the thermal land size and your board design rules allow. stencil pattern design reflowed solder joints on the perimeter i/o lands should have about a 50 m to 75 m (2mils to 3mils) standoff height. the solder paste stencil design is the first step in developing optimized, reliable solder joints. stencil aperture size to land size ratio should typically be 1:1. the aperture width may be reduced slightly to help prevent solder bridging between adjacent i/o lands. to reduce solder paste volume on the larger thermal lands, it is recommended that an array of smaller apertures be used instead of one large aperture. it is recommended that the stencil printing area cover 50% to 80% of the pcb layout pattern. a typical solder stencil pattern is shown in the package outline drawing on page 28 . the gap width between pad to pad is 0.6mm. the user should consider the symmetry of the whole stencil pattern when designing its pads. a laser cut, stainless steel stencil with electropolished trapezoidal walls is recommended. electropolishing ?smooths? the aperture walls resulting in reduced surface friction and better paste release which reduces voids. using a trapezoidal section aperture (tsa) also promotes paste release and forms a "brick like" paste deposit that assists in firm component placement. a 0.1mm to 0.15mm stencil thickness is recommended for this large pitch (1.3mm) hda. figure 43. recommended layout
ISL8216M 23 fn8607.2 may 9, 2014 submit document f eedbac k reflow parameters due to the low mount height of the hda, "no clean" type 3 solder paste per ansi/j-std-005 is recommended. nitrogen purge is also recommended during reflow. a system board reflow profile depends on the thermal mass of the entire populated board, so it is not practical to define a specific soldering profile just for the hda. the profile given in figure 44 is provided as a guideline, to be customized for varying manufacturing practices and applications. figure 44. typical reflow profile 0 300 100 150 200 250 350 0 50 100 150 200 250 300 temperature (c) slow ramp and soak from +100c to +180c for 90s~120s ramp rate 1.5c from +70c to +90c peak temperature +230c~+245c; keep about 30s above +220c duration (s)
ISL8216M 24 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www .int er sil.com/en/suppor t/q ualandreliability .html intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www .int er sil.com fn8607.2 may 9, 2014 for additional products, see www .int er sil.com/en/pr oducts.html submit document f eedbac k about intersil intersil corporation is a leading provider of innovative power management and precision analog solutions. the company's product s address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www .int er sil.com . you may report errors or suggestions for improving this datasheet by visiting www .int er sil.com/ask . reliability reports are also available from our website at www .int er sil.com/suppor t revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change may 9, 2014 fn8607.2 page 1: added ?compliant with ?en55022 class b (see an1907)? bullet to features section. page 3: removed redundant line that was on the ?internal block diagram?. march 14, 2014 fn8607.1 updated the following in the ?electrical specifications? on page 6, oscillator section: frequency range, min from 100 to 200 sync frequency range, min from 100 to 200 february 10, 2014 fn8607.0 initial release
ISL8216M 25 fn8607.2 may 9, 2014 submit document f eedbac k package outline drawing y22.15x15 22 i/o 15mmx15mmx3.6mm custom hda module rev 2, 9/13 14 7 13 11 12 9 10 8 5 642 31 0.10 c (7.5x7.5) index area terminal #a1 0.10 c2x 2x 15.00 15.00 a b bottom view side view top view detail b all tolerances 0.10mm, unless otherwise noted. represents the basic land grid pitch. 3. 2. all dimensions are in millimeters. 1. notes: the total number of smaller i/o pads is 17. all 17 i/o?s are centered in a fixed row and column matrix at 1.0mm pitch bsc. dimensioning and tolerancing per asme y14.5m-1994. tolerance for exposed dap edge location dimension. 4. 5. 6. 3.7 max max 0.025 c seating plane 0.10 c 0.08 c datum a see detail b 13.60 0.15 f f f c a b 13.60 0.15 f f f c a b datum b 7.30 see detail a c = 0.35 pin 1 indicator 13.00 5.00 a b c d e f 1.50 0.50 0.10 c a b 0.10 c 17x (0.600.05) 4 3 1.00 17x (0.600.05) 4 1.00 1.00 1.00 3 terminal tip detail a y22.15x15
ISL8216M 26 fn8607.2 may 9, 2014 submit document f eedbac k 0.60 2.00 2.30 3.00 4.30 3.70 3.60 3.30 2.30 3.00 3.60 4.30 7.30 3.00 4.30 a1 3.00 centerline position details for the 5 exposed daps bottom view dimensional details for the 5 exposed pads bottom view 4.35 3.30 6.15 3.65 4.65 6.50 4.65 5.15 0.35 a1 3.15 4.00 details for the 5 expose pads
ISL8216M 27 fn8607.2 may 9, 2014 submit document f eedbac k 1.80 3.20 0.00 0.50 1.20 1.80 2.20 2.80 3.20 3.80 4.20 4.80 5.20 5.80 6.20 6.80 7.50 7.50 0.00 7.50 6.80 6.20 4.80 4.20 2.80 2.20 1.50 0.80 1.50 0.20 2.20 2.50 2.80 5.50 6.20 6.80 7.50 0.00 0.80 4.80 5.50 6.80 7.50 0.00 1.80 2.50 6.80 7.50 6.80 1.80 2.50 5.50 6.20 7.50 0.20 0.80 1.50 3.20 3.80 4.20 4.80 6.20 6.80 7.50 6.80 3.50 4.20 4.80 terminal and pad edge details bottom view terminal and pad edge details
ISL8216M 28 fn8607.2 may 9, 2014 submit document f eedbac k 7.50 7.50 7.50 7.50 7.50 7.50 7.50 7.50 6.79 6.22 4.79 4.22 3.79 3.22 0.00 0.00 0.79 1.30 0.22 0.10 0.79 1.30 0.22 0.10 2.22 2.79 4.22 4.79 6.22 6.79 6.79 6.22 5.30 4.10 3.90 2.79 2.22 2.70 6.79 6.22 5.79 5.22 4.79 4.22 3.79 3.22 2.79 2.22 1.79 1.22 1.30 0.45 0.25 0.60 0.18 1.83 2.15 4.15 4.48 6.48 6.45 4.85 4.45 2.85 1.45 0.15 0.55 1.45 2.15 4.00 2.48 2.75 3.68 3.75 4.15 5.15 5.20 5.55 6.25 6.55 6.75 5.40 5.65 6.65 2.10 3.15 4.30 4.50 3.45 4.55 4.79 4.22 7.50 7.50 7.50 7.50 7.50 7.50 7.50 7.50 4.50 6.50 3.50 0.00 2.50 4.50 6.50 2.50 0.88 0.00 0.17 0.50 0.50 6.15 5.50 6.50 4.50 3.50 2.50 0.70 0.70 3.30 4.70 1.50 6.05 4.65 3.25 4.60 3.08 1.35 1.00 0.65 3.65 5.65 5.48 3.15 0.83 6.19 4.11 5.15 2.63 3.98 4.98 3.88 4.50 suggested stencil opening center position top view suggested stencil opening edge position top view stencils
ISL8216M 29 fn8607.2 may 9, 2014 submit document f eedbac k 1.80 3.20 0.00 0.50 1.20 1.80 2.20 2.80 3.20 3.80 4.20 4.80 5.20 5.80 6.20 6.80 7.50 7.50 0.00 7.50 6.80 6.20 4.80 4.20 2.80 2.20 1.50 1.50 0.20 2.20 2.50 2.80 5.50 6.20 6.80 7.50 0.00 0.80 4.80 5.50 6.80 7.50 0.00 1.80 2.50 6.80 7.50 6.80 1.80 2.50 5.50 6.20 7.50 0.20 0.80 1.50 3.20 3.80 4.20 4.80 6.20 6.80 7.50 6.80 3.50 4.20 4.80 pcb land pattern 0.80 pcb land pattern

▲Up To Search▲

Price & Availability of ISL8216M

	To Download ISL8216M Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .